Method of making a MOS transistor

ABSTRACT

A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a metal silicide. The disclosed MOS transistor fabricating method comprises providing a semiconductor substrate further comprising a polysilicon gate electrode with a silicide layer thereon, a spacer, and source and drain regions with LDD regions; forming an insulating layer on the area of the substrate; polishing the insulating layer so that the top of the polysilicon gate electrode can be exposed; etching some part of the insulating layer and the spacer so that both lateral walls of the polysilicon gate electrode can be exposed; forming a metal layer on the substrate resulted from the preceding step so that the polysilicon gate electrode can be covered with the metal layer; and transforming completely the polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process.

RELATED APPLICATIONS

This is a divisional of U.S. application Ser. No. 10/627,059, filed Jul.25, 2003.

TECHNICAL FIELD

The present disclosure relates to semiconductors and, more particularly,to a method of making a metal-oxide-semiconductor (MOS) transistor.

BACKGROUND

As MOS devices have been integrated at a rapid speed, an existingprocess using polysilicon as a gate electrode has caused many problemssuch as high gate resistance, depletion of polysilicon, and boronpenetration into a channel area. Such problems have been solved by aprocess including a metal gate electrode. However, the process offorming a metal gate has caused new problems, such as difficulty inetching a metal and limitations in enduring high-temperature thermaltreatment.

Accordingly, a damascene process has been proposed to solve suchproblems. However, the damascene process uses a chemical mechanicalpolishing (CMP) process repeatedly, thereby complicating the process,although CMP solved the problems of an existing metal gate process.

To obviate such process complexity, a method of making a MOS transistorusing a single CMP process has been proposed. Reference will now be madein detail to a known MOS transistor fabricating method using a singleCMP process, examples of which are illustrated in the accompanyingdrawings. FIGS. 1 a through 1 c are cross-sectional views illustrating aMOS transistor fabricated according to a known process. Referring toFIG. 1 a, a polysilicon gate electrode 5 is formed on a semiconductorsubstrate 1, and lightly doped drain (LDD) regions 2 are formed on thesubstrate 1 at both sides of the polysilicon gate electrode 5. Then, aspacer 6 is formed on both lateral walls of the polysilicon gateelectrode 5, and source and drain regions 3 are formed on the substrate1 at both sides of the polysilicon gate electrode 5. Subsequently, asilicide layer 7 is coated on the top of the polysilicon gate electrode5 and the surface of the source and drain regions 3, and a nitride layer8 is formed on the entire area of the semiconductor substrate having thesource and drain regions 3 and the LDD regions 2 so that the polysilicongate electrode 5 can be covered. Next, an insulating layer 9 is formedon the nitride layer 8. The nitride layer 8 is usually between about 300and about 1000 Å in thickness, and is formed by a plasma enhancedchemical vapor deposition (PECVD) process.

Next, referring to FIG. 1 b, the nitride layer 8 and the insulatinglayer 9 are polished by a CMP process until the top of the polysilicongate electrode 5 is exposed. The CMP process is performed by overpolishing so that the top of the polysilicon gate electrode 5, inuniform thickness, can be exposed completely. Then, a metal layer 10 isdeposited, in uniform thickness, on the exposed region of thepolysilicon gate electrode 5, the nitride layer 8 and the insulatinglayer 9. The metal layer 10 is usually less than about 1000 Å and, insome cases, may be between about 500 and about 1000 Å in thickness. Themetal layer 10 may be a multilayer of Ti/TiN, Co/TiN, or Co/Ti/TiN.

Referring to FIG. 1 c, a thermal treatment is performed on the substratehaving the metal layer 10 to transform the polysilicon gate electrode 5into a metal silicide gate electrode 7. The thermal treatment processmay be performed through two steps, i.e., a first step at a temperatureof about 400° C. to about 600° C., and a second step using a rapidthermal process (RTP) at a temperature of about 800° C. to about 1000°C. Subsequently, the residual metal layer, which has not reacted, isremoved.

However, such a method of fabricating a MOS transistor cannot completelytransform the polysilicon gate electrode 5 into the metal silicide gateelectrode 7 because the area where the metal of the metal layer can bediffused while performing the thermal treatment is insufficient due tothe small contact area between the polysilicon gate electrode 5 and themetal layer 10. To obviate such a disadvantage, the thermal treatmentprocess to form the metal silicide gate electrode 7 has to be performedfor many hours. However, such a long thermal treatment may causedeterioration of device characteristics because an impurity implanted insource and drain regions 3 may be diffused irregularly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a through 1 c are cross-sectional views illustrating a knownprocess of fabricating a MOS transistor.

FIGS. 2 a through 2 e are cross-sectional views illustrating thedisclosed process of fabricating a MOS transistor.

DETAILED DESCRIPTION

As disclosed herein, a polysilicon gate electrode may be completelytransformed into a metal silicide gate electrode by performing a thermaltreatment process for a short time because the exposed area of thepolysilicon gate electrode, which is in contact with the metal layer, isincreased prior to performing the silicide process.

Referring to the example of FIG. 2 a, a gate oxide 24 and a polysilicongate electrode 25 are formed on a semiconductor substrate 21. Then, LDDregions 22 are formed on the surface of the substrate at both sides ofthe polysilicon gate electrode 25. A spacer 26 is formed on both lateralwalls of the polysilicon gate electrode 25, and source and drain regions23 are formed on the surface of the substrate at both sides of thepolysilicon gate electrode 25 including the spacer 26. A self-alignedsilicide layer 27 is formed on the top of the polysilicon gate electrode25 and on the surface of the source and drain regions 23.

As shown in the example of FIG. 2 b, the entire area of thesemiconductor substrate 21 including the polysilicon gate electrode 25and source and drain regions 23 are coated with an insulating layer 29.The insulating layer 29 may be formed by using the same material as thespacer 26.

Referring to FIG. 2 c, the insulating layer 29 is polished by, forexample, a CMP process until the top of the polysilicon gate electrode25 is exposed. Then, some part of the insulating layer 29 and the spacer26 are etched by the method of dry-etching and/or wet-etching until thepolysilicon gate electrode 25 is exposed to more than about ⅔ of itsheight. In one particular example, the polysilicon gate electrode 25 isexposed from about {fraction (4/6)} to about ⅚ of its height.Accordingly, as explained below, as the exposed area of the polysilicongate electrode 25 is increased, the contact area between the polysilicongate electrode 25 and a metal layer 30 is expanded, and the polysilicongate electrode 25 can be completely transformed into a metal silicidegate electrode 31.

Next, referring to FIG. 2 d, the entire area of semiconductor substrateshown in FIG. 2 c is coated with a metal layer 30 of uniform thickness.In one example, the metal layer 30 is less than 1000 Å thick and may be,for example, between about 500 and about 1000 Å in thickness. The metallayer 30 may be a multilayer comprising transition metals and theiralloys such as, for example, Ti/TiN, Co/TiN, or Co/Ti/TiN.

Finally, referring to FIG. 2 e, a thermal treatment process is performedon the substrate coated with the metal layer 30 to transform completelythe polysilicon gate electrode 25 into a metal silicide gate electrode31. The thermal treatment may be a rapid thermal process and may beperformed through two steps, i.e., a first step at a temperature ofabout 400° C. to about 600° C., and a second step using RTP at atemperature of about 800° C. to about 1000° C.

As described previously, the contact area between the metal layer andthe polysilicon gate electrode is increased because the exposed area ofthe polysilicon gate electrode is extended or expanded prior to theformation of the metal layer. Therefore, the polysilicon gate electrodereacts actively with the metal layer, and can be completely transformedinto the metal silicide electrode. Subsequently, the residual metallayer that has not reacted is removed to complete a disclosed MOStransistor. Accordingly, the disclosed techniques can completelytransform the polysilicon gate electrode into the metal silicideelectrode through a brief thermal treatment process by extending thecontact area between the polysilicide gate electrode and the metal layerprior to the formation of the metal silicide.

The disclosed techniques may be used to produce MOS transistors, eachhaving a gate oxide, a spacer and a gate electrode the top and some partof lateral walls of which are exposed. In addition, the MOS transistorfurther includes a metal layer that is made of transition metals andtheir alloys. The disclosed MOS transistors each have a gate electrodethat is fully silicided.

Although certain apparatus constructed in accordance with the teachingsof the invention have been described herein, the scope of coverage ofthis patent is not limited thereto. On the contrary, this patent coversevery apparatus, method and article of manufacture fairly falling withinthe scope of the appended claims either literally or under the doctrineof equivalents.

1. A MOS transistor comprising: a gate oxide; a spacer; and a gateelectrode including a top and lateral walls, wherein the top and somepart of lateral walls are exposed.
 2. A MOS transistor as defined byclaim 7, wherein said gate electrode is fully silicided.
 3. A MOStransistor as defined by claim 7 further comprising a metal layercomprising transition metals and their alloys, said metal layer beingformed on a surface of said gate electrode.
 4. A MOS transistor asdefined by claim 9, wherein said gate electrode is fully silicided.
 5. AMOS transistor as defined by claim 9, wherein said metal layer has athickness between about 500 Å and about 1000 Å.
 6. A MOS transistor asdefined by claim 9, wherein said metal layer comprises one or more ofTi/TiN, Co/TiN and Co/Ti/TiN.
 7. A MOS transistor as defined by claim12, wherein said metal layer has a thickness between about 500 Å andabout 1000 Å.